PACKET RADIO: Memory ARQ

Steve Wolf, W8IZ@W8IZ


(This text from the W8IZ packet radio bulletin

board. It's formatted to fit a 80 character screen.)


SB PACTOR @ ALLUS < VE7CIZ $146_VE7CIZ
The "real" PACTOR
R:931015/0439z 4806@NO8M.#NEOH.OH.USA.NA
...
R:931009/1834 146@VE7CIZ.#VANC.BC.CAN.NA
To All Radio Amateurs,
Here is some information on the difference between the memory
ARQ of the PACTOR-Controller (PTC) and other PACTOR software
without memory ARQ or with so-called "digital memory ARQ".
                                                                   
In conventional ARQ systems the TX has to repeat a packet until
the whole information, or at least the bit pattern of major parts
of it have been received completely, and error free. It is evident
that the probability of receiving a packet correctly, dramatically
decreases with lower S/N ratio (SNR).
VE7CIZ, QRA WA2MFY/SYS/1:
                                                                   
Some ways to maintain a contact in that case are to shorten the
packet length or to apply error correcting codes which in turn
will greatly reduce maximum traffic speeds when conditions are
good.
                                                                   
Another method, known as "intelligent reconstruction", combines 
error free received parts of different transmissions of the same 
data packet, in various ways checking if the result passes the
corresponding redundancy test.
                                                                     
A similar method, the so-called "digital memory ARQ", reconstructs
information by digital addition of several packets. However, a
digital converter is only able to emulate a 1-bit ADC, thus
meaning that there is only a small chance of increasing speed
in poor conditions. If the SNR is falling short of a certain
"threshold", and only a few bits are received in a correct
pattern with every transmission period, the link can hardly
be improved this way, even with a lot of repetitions.
                                                                  
Real memory ARQ always requires an analog to digital converter
(ADC). In the SCS PACTOR-controller (PTC), as well as the
version of PacComm, samples are taken from the PSK-demodulator
low-pass filter output with the aid of an 8-bit AD-converter.
This means that the information, whether a signal is e.g.,
100mv or 1mv over the converter threshold, is not lost like in
digital systems, but is used to reconstruct the data.
Assuming white Gaussian noise, this accumulation method will
maintain an HF link at a lower SNR than any digital system,
because the whole bit pattern of a packet can be obtained
using the information of several transmission periods. No
correct received parts are needed. Furthermore, since shift
levels are toggled with every transmission, even constant
interfering signals within the receiver's passband will not
affect the mean value. Besides that, the ADC can be used to
emulate adaptive filters and therefore save additional hardware.
                                                                    
The PACTOR protocol is especially designed to support memory 
ARQ (e.g. the packet header is inverted with every new information
packet to prevent accumulation of old requested packets).
So everybody who implements PACTOR has to use an ADC in order
to keep the high standard of PACTOR.
                                                                 
After watching some QSO's of OM's running software without an
ADC and realizing that there has been mostly very slow traffic
with 100 baud and many repetitions in quite good condiitons, 
I am afraid that there are some major bugs in the phasing
correction and speed adaptation software, besides the missing
memory ARQ. This may be prejudicial to the PACTOR system in
general.
                                                                   
I hope this information answered some questions sufficiently.
Best 73 de Tom, DL2FAK (edited by Julius W9UWE).

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